Hari Vijay Venkatanarayanan

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A new jitter reduction circuit is proposed for reducing the timing jitter in a serializer-deserializer (SERDES). Instead of using elaborate hardware to calculate the jitter, we use the jittered signal's autocorrelation to remove the jitter. The motivation for this work was to provide a reduced jitter phase-locked loop (PLL), so that incorporating a built-in(More)
Mixed-signal systems-on-a-chip (SoCs) are tested using the IEEE 1149.4 analog test bus, but the area overhead and test time are high. We present a new mixed-signal SoC test architecture , which uses the circuit components along with design-for-testability (DFT) hardware. Rather than building a custom ana-log test waveform generator on chip exclusively for(More)
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