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The signals used in UMTS have wide band-width and high crest factors. Circuit designers use sinusoids to design and simulate their building blocks. Formulas are presented relating the various distortion effects of the W-CDMA signals like adjacent channel leakage ratio (ACLR), cross modulation or intermodulation to well-known lin-earity measures like input(More)
A zero-IF front-end consisting of an I/Q down-conversion mixer, broadband I/Q-generation, fully-integrated VCO, dual-modulus prescaler, low-noise baseband buffer and blocking filter is presented. Integrated in a 75 GHz f/sub t/ BiCMOS technology with 0.35 /spl mu/m CMOS it draws 33 mA from a 2.7 V supply. Extremely low local-oscillator leakage of -95 dBm(More)
A multi-standard, multi-band fully-integrated interstage filter-free receiver with integrated auto-centered TX leakage filtering is fabricated in a 65 nm CMOS technology. The measured TX selectivity in UMTS band II is 9.1 dB, the receiver gain at 1.96 GHz is 54.1 dB, and NF is 3.68 dB. The 0.5 dB reference sensitivity degradation caused by TX leakage is(More)
A zero-IF receiver for UMTS realized by using an advanced 0.35 /spl mu/m SiGe BiCMOS process with 75 GHz transit frequency is presented. The focal point is the analog baseband chain consisting of a low-noise buffer (LNB), a fully integrated channel selection filter, programmable gain amplifiers (PGA) and circuits to reduce the effects of DC-offsets. The(More)
In this paper, a 28nm radio frequency (RF) complementary metal-oxide-semiconductor (CMOS) power amplifier (PA) is presented. It was designed to meet 3GPP TS 36.101 V10.10.0 requirements for Long Term Evolution (LTE). The design was tested on board and has full onchip matching. Furthermore, the biasing for class-AB is also implemented on chip. The maximum(More)
We present a linear two-stage power amplifier (PA) for UMTS terrestrial radio access (UTRA) applications. The PA has been designed using a standard 28-nm complementary metal-oxide-semiconductor process. It includes an on-chip input matching network, a predriver stage, and an on-chip output matching network. Additional process-voltage-temperature(More)
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