Hao-Yueh Hsieh

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In this paper, we study the problem of block and I/O buffer placement in flip-chip design. The goal of the problem is to simultaneously minimize the total path delay and the total skew of all input/output signals. We present two simple yet effective algorithms for the problem. Both algorithms place blocks to minimize the total path delay, and place I/O(More)
In this paper, we present a simple yet effective technique to improve an existing methodology for system-level point-to-point communication architecture synthesis in SOC design. The technique enables the existing methodology to simultaneously consider the chip area, communication energy, and wirelength to evaluate a candidate communication architecture(More)
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