Hansruedi Heeb

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With ever increasing clock frequencies, accurate 3-D interconnect analysis in chips and packages is becoming a necessity. The retarded partial element equivalent circuit (rPEEC) method has been successfully applied to 3-D analysis but for large problems at becomes expensive in CPU and memory usage, and in time domain it sometimes has numerical problems.(More)
The time-domain modeling of the connections in a high-speed computer is such of a complexity that practical problems can only be solved using suitable approximations. Presented are the results of a time-domain modeling work where a novel and faster representation of the capacitances has been developed. Instead of a circuit with O(n/sup 2/) capacitances(More)
A growing need exists for electrical interconnect analysis (EIA) for chips, packages and printed circuit boards. In this short tutorial we review key issues regarding EIA for VLSI parasitic circuits. We give a general introduction of important aspects for technologies with different performances and then we review some issues of concern for state of the art(More)
Full-wave electromagnetic modeling is used increasingly to model the properties of high speed interconnect or to predict electromagnetic interference. Retarded partial element equivalent circuit (rPEEC) models provide a way to simulate with full-wave accuracy in time and frequency domain without leaving the level of circuit simulation. This paper presents a(More)
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