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In LOTOS, a system is specified as a behaviour expression describing the externally observable behaviour of the system in terms of possible sequences of interactions between the system and its environment. The desired control flow and data flow that must be established by a possible implementation of the system are specified in the behaviour expression as(More)
A data flow oriented test selection method for selectively generating abstract tests from a LOTOS specification is presented. This method is based on static data flow analysis to identify maximal IO-df-chains, which exhibit the associations between each specification output and those specification inputs that influence the output through definitions and(More)
A relief strategy called fair reachability analysis [5, 7, 11] is extended for the verification of daisy-chain protocols, which are defined in the communicating finite state machine model as networks of n ≥ 2 processes with a bidirectional, serial link structure. Fair reachability analysis is shown to decide the deadlock detection problem for daisy-chain(More)
A methodology is presented for writing modern SystemVerilog testbenches that can be used not only for software simulation, but especially for hardware-assisted acceleration. The methodology is founded on a transaction-based co-emulation approach and enables truly single source, fully IEEE 1800 SystemVerilog compliant, transaction-level testbenches that work(More)
he communicating finite state machine (CFSM) model is one of the most widely used models for specifying and verifying communications protocols. In this model, a protocol is specified as a network of two or more processes exchanging messages over error-free simplex channels, where each process is a finite state machine (FSM) and each simplex channel is a(More)