Key characteristics of newly emerging IC technologies render the traditional concept of die size minimization and traditional "design rules" insufficient to handle the design-manufacturing interface. This tutorial surveys the design and process characteristics relevant to the manufacturability of submicron ICs. The discussion also covers analysis of design… (More)
Owing to rapid changes of IC technologies, traditionaldesign rule checking is becoming inadequate to assure satisfactorylevels of IC manufacturability. This paper describes a newcomputer supported design analysis environment that improvesthe efficiency of manufacturability assessment of new products.This environment, called MAPEX 2, is described in the… (More)
A sound IC design methodology must be supported by adequate manufacturability assessment tools. These tools should assist a designer in predicting IC manufacturing cost in as early a design stage as possible. In this paper a yield model is proposed that takes as input a standard cell netlist and produces as output a yield estimate without performing… (More)
Traditional VLSI design objectives are to minimize time-to-first-silicon while maximizing performance. Such objectives lead to designs which are not optimum from a manufacturability perspective. The objective of this paper is to illustrate the above claim by performing performance/ manufacturability tradeoff analysis. The basis for such an analysis, in… (More)
This paper illustrates via examples problems at the design-manufacturing interface that exist in the IC industry today, and the ability of the YAN/PODEMA framework in solving these problems. The need for further development of the framework is also emphasized.
This paper proposes a vision for a new research domain emerging on the interface between design and manufacturing of VLSI circuits. The key objective of this domain is the minimization of the mismatch between design and manufacturing which is rapidly growing with the increase in complexity of VLSI designs and IC technologies. This broad objective is… (More)
This paper describes DFT/DFD/DFM strategies implemented on a 40Gbps framer chip. The device is a 1500 pin, over 10M gate SoC with multiple PLLs/DLLs and 2.5GHz IOs. Some novel techniques were required to ensure quality and manufacturability.