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—Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and running them on an embedded multi-core processor, which enables combining the requirements for(More)
—Hard real-time applications in safety-critical domains – namely avionics, automotive, and machinery – require high-performance and timing analysability. We present research results of the parallelisation and WCET analysis of an industrial hard real-time application, i.e. the control code of a large drilling machine from BAUER Maschinen GmbH. We reached a(More)
The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore processor. A pattern-supported parallelization approach was developed to ease sequential to parallel program transformation based on(More)
Applications in industry often have grown and improved over many years. Since their performance demands increase, they also need to benefit from the availability of multi-core processors. However, a reimplementation from scratch and even a restructuring of these industrial applications is very expensive, often due to high certification efforts. Therefore, a(More)
SUMMARY Finding the optimal position for the individual cells (also called functional modules) on the chip surface is an important and diicult step in the design of integrated circuits. This paper deals with the problem of relative placement, that is the minimization of a quadratic functional with large, sparse, positive deenite system matrix. The basic(More)
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