A method for the fully automatic equivalence verification of a design before and after the scheduling step of high-level synthesis is presented. The technique is applicable to the results of advanced scheduling methods like AFAP and DLS, which work on cyclic control flows, as well as to pipelined designs.
A method of formally correct synthesis is presented and applied to the automatic construction of pipelined processors. The approach is based on a small set of correctness-preserving transformations that are eeciently cross-checked by an independent formal veriication tool. Basic pipeline strategies as well as automatic post-synthesis veriication are… (More)
A new approach for the automatic equivalence checking of behavioral or structural descriptions of designs with complex control is presented. The veriication tool combines symbolic simulation with a hierarchy of equivalence checking methods, including decision-diagram based techniques, with increasing accuracy in order to optimize overall veriication time… (More)
Formal veriication tools must often cope with large memory sizes and indirect addressing. This paper presents a new approach of how to handle memory operations in the symbolic simulation of designs with complex control logic, e.g., processors. The simulator is currently used to check the equivalence of two processor descriptions with distinct order of… (More)
Property-based design has multiple applications in the domain of formal verification. We have developed a tool capable of automatically generating an exact implementation from a set of finite PSL properties.
A method of formally correct synthesis is presented, and applied to the automatic construction of pipelined processors. The method is based on a repertoire of elementary correctness-preserving transformations which are eeciently cross-checked by an independent formal veriication tool. Basic pipelining strategies as well as automatic post-synthesis… (More)