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A new approach for the automatic equivalence checking of behavioral or structural descriptions of designs with complex control is presented. The veriication tool combines symbolic simulation with a hierarchy of equivalence checking methods, including decision-diagram based techniques, with increasing accuracy in order to optimize overall veriication time(More)
Formal veriication tools must often cope with large memory sizes and indirect addressing. This paper presents a new approach of how to handle memory operations in the symbolic simulation of designs with complex control logic, e.g., processors. The simulator is currently used to check the equivalence of two processor descriptions with distinct order of(More)
11 On-line monitoring of properties built on regular expressions sequences 183 Katell Morin-Allory, Dominique Borrione 12 Observer-based verification using introspection 195 Abstract The verification of a design's adherence to its specification has been and still is a major problem within the EDA community. Multiple issues like completeness, consistency,(More)
This paper defines a quantitative metric of the completeness of a formal specification. A "good" (formal) specification is already needed in the beginning of the development process to prevent cost-intensive corrections of errors found in the late phases of a design process. A quantitative analysis method is presented to evaluate whether a specification is(More)