A method for the fully automatic equivalence verification of a design before and after the scheduling step of high-level synthesis is presented. The technique is applicable to the results of advanced scheduling methods like AFAP and DLS, which work on cyclic control flows, as well as to pipelined designs.
A new approach for the automatic equivalence checking of behavioral or structural descriptions of designs with complex control is presented. The veriication tool combines symbolic simulation with a hierarchy of equivalence checking methods, including decision-diagram based techniques, with increasing accuracy in order to optimize overall veriication time… (More)
Property-based design has multiple applications in the domain of formal verification. We have developed a tool capable of automatically generating an exact implementation from a set of finite PSL properties.
—Property-based synthesis has become a more prominent topic during the last years, being used in multiple areas like e.g. formal verification and design automation. We will show how a property-based formal specification of a cache controller for a MIPS core can be used to automatically generate a functional implementation of that controller and how… (More)
Most timing-verifiers are analytical tools that determine, e.g., the delays on all paths, etc. This paper presents a completely different approach: timing-verification is performed by means of the formal transformation of CHDL descriptions. The principles of this procedure are presented and performance results of an implementation are given.
Formal veriication tools must often cope with large memory sizes and indirect addressing. This paper presents a new approach of how to handle memory operations in the symbolic simulation of designs with complex control logic, e.g., processors. The simulator is currently used to check the equivalence of two processor descriptions with distinct order of… (More)