Hans Eveking

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A new approach for the automatic equivalence checking of behavioral or structural descriptions of designs with complex control is presented. The veriication tool combines symbolic simulation with a hierarchy of equivalence checking methods, including decision-diagram based techniques, with increasing accuracy in order to optimize overall veriication time(More)
ACYCLIC DESCRIPTIONS WITH COMPLEX BRANCHING LOGIC Holger Hinrichsen Gerd Ritter Hans Eveking Dept. of Electrical and Computer Engineering Darmstadt University of Technology, D-64283 Darmstadt, Germany fhinrichsen/ritter/evekingg@rs.tu-darmstadt.de Abstract A heuristic method for the false-path elimination and the simpli cation of sequential acyclic(More)
Formal veriication tools must often cope with large memory sizes and indirect addressing. This paper presents a new approach of how to handle memory operations in the symbolic simulation of designs with complex control logic, e.g., processors. The simulator is currently used to check the equivalence of two processor descriptions with distinct order of(More)
This paper defines a quantitative metric of the completeness of a formal specification. A "good" (formal) specification is already needed in the beginning of the development process to prevent cost-intensive corrections of errors found in the late phases of a design process. A quantitative analysis method is presented to evaluate whether a specification is(More)