Learn More
In this paper, we present the system design of an integrated receiver for the next generation high-speed mobile data communications based on OFDM. First an overview of the OFDM system suitable for mobile communications is described. The effects of non-ideal transmission conditions of the OFDM system including channel estimation errors, symbol timing offset,(More)
An OFDM receiver ASIC specifically targeting mobile applications has been designed and fabricated. The receiver ASIC incorporates the digital front-end receiver, pre/post-FFT processing units, a 1024-point complex (I)FFT processor, channel estimator and corrector, all digital synchronization loops, and control and configuration interface. In this paper we(More)
The increased competition to deliver broadband data to the home (including GPON and VDSL) is motivating cable providers to deliver data rates which far exceed what is presently available based on the DOCSIS 1.x and DOCSIS 2.0 standards. The DOCSIS 3.0 standard provides this bandwidth increase as well as additional flexibility, where higher data throughput(More)
An OFDM receiver ASIC targeting cellular terminals has been designed and fabricated in 0.18 /spl mu/m CMOS. The receiver incorporates a front-end receiver, pre/post-FFT processing units, a 1024-point complex (I)FFT processor, a channel estimator and corrector, all digital synchronization loops, and a control and configuration interface. Low power circuit(More)
An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz(More)
A silicon implementation of a dual antenna mobile station modem for 3G WCDMA is presented. Diversity processing is used to support data rates up to 2 Mb/s while reducing power consumption. An average SNR improvement of 7 dB has been observed yielding up to a 4x increase in capacity with no change to the exisiting network infrastructure.
The proper choice of modulation and detection schemes to enable high-speed wireless indoor data communications has been the subject of extensive study. Of particular interest to ASIC designers is the complexity, cost and power dissipation of the analog and digital processing elements associated with such systems. This paper presents a side-by-side(More)
The design and implementation of a baseband wide-band code-division multiple access (WCDMA) dual-antenna mobile terminal system-on-a-chip (SoC) is presented in this paper. Spatial diversity processing mitigates wireless channel impairments and is a key enabling technology for WCDMA to support high quality of service at high data rates and capacity. The SoC(More)
In this paper algorithmic and implementation innovations for a novel diversity processing based WCDMA synchronization system are presented. The system employs a dual antenna front end system and a three stage pipelined synchronization technique to achieve slot, frame and code synchronization. The slot boundary section employs a hybrid matched(More)
This paper presents a complete study and characterization of a real-time frequency-hopped, frequency shift-keyed testbed capable of transmitting data at 160 kb/s, with hopping rates of up to 80 Khops/s operating in the 900 MHz band. The system provides the highest hopping rate reported to date and sets a new trend for FHSS communications with superior low(More)