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Applications in High Performance Computing (HPC) cloud are characterized by large cache resource consumption due to large-scale inputs and intensive communications, which creates serious Shared Last Level cache (SLLC) performance bottleneck. Current system software stacks are not efficient in addressing this issue among virtual machines at the hypervisor(More)
Conventional geometric design techniques based on B-splines and NURBS often require tedious control-point manipulation and/or painstaking constraint speci®cation via unnatural mouse-based computer interfaces. In this paper, we propose a novel and natural haptic interface and present a physics-based geometric modeling approach that facilitates interactive(More)
Emerging non-volatile memory (NVM) technologies are promising alternatives to DRAM. However, the write inefficiency associated with NVM brings significant challenges to the last-level cache (LLC) replacement design. LLC replacement policies in the context of DRAM hardly focus on writeback optimization. Based on the observation that writeback to NVM(More)
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