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It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially(More)
In this paper, the NBTI induced dynamic V th variability in nano-scaled MOSFETs is comprehensively studied. In addition to the device-to-device variation (DDV) of NBTI degradation, the non-negligible cycle-to-cycle variation (CCV) due to the random occupation of trap states in each operation cycle is observed for the first time. By using the statistical(More)
In this paper, a new class of layout dependent effects (LDE)—the time-dependent layout dependency due to device aging, is reported for the first time. The BTI and HCI degradation in nanoscale HKMG devices are experimentally found to be sensitive to layout configurations, even biased at the same stress condition. This new effect of layout dependent aging(More)
In this paper, the major physical effects caused by gate oxide traps in MOSFETs have been integrated for the first time by a proposed unified approach in realistic manners based on industry-standard EDA tools, aiming at practical trap-aware device/circuit co-design. The recently-found AC or transient effects of traps and the interplays with manufacturing(More)
In nano-MOSFETs, single trap induced V<sub>th</sub> degradation becomes more serious with the scaling of the gate area, which has attracted increasing attention. The single-trap response under NBTI stress can severely impact the predictions of degradation. Based on the statistical trap-response (STR) characterizing method, the time-dependent statistics of(More)
In this paper, a more CMOS process compatible scheme to tune the Schottky Barrier Height (SBH) of NiSi to electrons (&#x03C6;<sub>bn</sub>) by means of boron (B) dopant segregation (DS) technique is presented. This scheme consists of the following steps: (1) deposit Ni layers on Si substrate; (2) rapid thermal anneal (RTA1) at 300&#x00B0;C/60 s to form(More)
for Robust Device/Circuit Co-Design Shaofeng Guo, Ru Huang, Peng Hao, Mulong Luo, Pengpeng Ren, Jianping Wang, Weihai Bu, Jingang Wu, Waisum Wong, Scott Yu, Hanming Wu, Shiuh-Wuu Lee, Runsheng Wang, Yangyuan Wang 1 Key Laboratory of Microelectronic Devices and Circuits (MOE), Institute of Microelectronics, Peking University, Beijing 100871, China(More)
in Scaled High-κ/Metal-gate Technology for the nano-Reliability Era Pengpeng Ren, Runsheng Wang, Zhigang Ji, Peng Hao, Xiaobo Jiang, Shaofeng Guo, Mulong Luo, Meng Duan, Jian F. Zhang, Jianping Wang, Jinhua Liu, Weihai Bu, Jingang Wu, Waisum Wong, Shaofeng Yu, Hanming Wu, Shiuh-Wuu Lee, Nuo Xu, Ru Huang Institute of Microelectronics, Peking University,(More)
In this paper, the statistical characteristics of complex RTN (both DC and AC) are experimentally studied for the first time, rather than limited case-by-case studies. It is found that, over 50% of RTN-states predicted by conventional theory are lost in actual complex RTN statistics. Based on the mechanisms of non-negligible trap interactions, new models(More)
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