HanBin Yoon

Learn More
As feature sizes continue to shrink, future chip multiprocessors are expected to integrate more and more cores on a single chip, increasing the aggregate demand for main memory capacity. Satisfying such a demand with DRAM alone may prove difficult due to DRAM scaling challenges. To address this problem, recent work has proposed using DRAM as a cache to(More)
Phase change memory (PCM) is a promising technology that can offer higher capacity than DRAM. Unfortunately, PCM's access latency and energy are higher than DRAM's and its endurance is lower. Many DRAM‐PCM hybrid memory systems use DRAM as a cache to PCM, to achieve the low access latency and energy, and high endurance of DRAM, while taking advantage of(More)
New phase-change memory (PCM) devices have low-access latencies (like DRAM) and high capacities (i.e., low cost per bit, like Flash). In addition to being able to scale to smaller cell sizes than DRAM, a PCM cell can also store multiple bits per cell (referred to as multilevel cell, or MLC), enabling even greater capacity per bit. However, reading and(More)
  • 1