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This paper presents an energy-efficient 3-stage Pseudo Single-phase family of Flip-flops (PSPFF) targeted for use in a 3GHz microprocessor in a 40nm, 0.9V CMOS technology. With latencies in line with the fast pulsed-latch and an average switching energy comparable to the master-slave flip-flop, PSPFF achieves an energy-delay product (EDP) which is 42% and… (More)
The following individuals read and discussed the thesis submitted by student Qawi IbnZayd Harvard, and they evaluated his presentation and response to questions during the final oral examination. They found that the student passed the final oral examination.