Hamed Sajjadi Kia

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We formulate the problem of energy consumption and reliability oriented application mapping on regular Network-on-Chip topologies. We propose a novel branch-and-bound based algorithm to solve this problem. Reliability is estimated by an efficient Monte Carlo algorithm based on the destruction spectrum of the network. Simulation results demonstrate that(More)
We propose to partition links in a network-on-chip into multiple segments and use spare wires at the level of each segment to address permanent errors due to manufacturing or wear out defects. Because different segments of the spare wires address different errors from different segments, the proposed reconfigurable link structure can tolerate a larger(More)
This paper studies and proposes heuristic algorithms to solve the problem of replicated server placement (RSP) with Quality of Service (QoS) constraints. Although there has been much work on RSP in multicast networks, in most of them a simplified replication model is used, therefore, their proposed solutions may not be applicable to real systems. In this(More)
In this paper, we propose a new fault-tolerant and congestion-aware adaptive routing algorithm for Networks-onChip (NoCs). The proposed algorithm is based on the balland-string model and employs a distributed approach based on partitioning of the regular NoC architecture into regions controlled by local monitoring units. Each local monitoring unit runs a(More)
We propose a novel cost-effective long-range NoC interconnect design based on current-mode signaling. The proposed CMOS based long-range link reduces the communication delay of long wires significantly without using traditional pipelined repeaters, making it a cost efficient alternative to wireless and optical interconnects. Spice simulations are performed(More)
We present an efficient FPGA based implementation of a dynamic simulation framework for Direct Torque Control (DTC) of induction motors. The merit of the proposed DTC emulation framework lies in that it is completely implemented within an FPGA, and therefore can be easily utilized for exploratory system optimizations. The high performance and low area(More)
Network on Chip (NoC) is an approach to designing the communication subsystem between IP cores in a System on a Chip (SoC). NoC improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs. The purpose of NOC is to solve the choke point in communication and the clock problem from architecture. Each route in NOC(More)
We propose a new circuit level reliability evaluation methodology. The proposed methodology is based on a divide and conquer approach, which enjoys the benefits of device level accuracy and of block level efficiency. At the core of the reliability estimation engine lies a Monte Carlo algorithm which works with failure times modeled as Weibull and lognormal(More)
In this paper, design and analysis of a programmable CMOS-based function generator circuit is presented. The proposed circuit implements trapezoidal and triangular functions with all parameters (slope, position, width and height) independently and continuously adjustable. The proposed circuit achieves higher speed compared to the available previous work by(More)
In this paper we propose a distributed routing algorithm for networks-on-chip (NoCs) that can dynamically detect permanent failures in NoC links and recalculate routing paths using healthy links. What sets the proposed methodology apart from the previous works is that it provides a better tradeoff point between the improvement in fault tolerance and(More)
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