Hakan Yazarel

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— S-TALIRO is a software toolbox that performs stochastic search for system trajectories that falsify real-time temporal logic specifications. S-TALIRO is founded on the notion of robustness of temporal logic specifications. In this paper, we present a dynamic programming algorithm for computing the robustness of temporal logic specifications with respect(More)
Mapping a set of feedback control components to executable code introduces errors due to a variety of factors such as discretization, computational delays, and scheduling policies. We argue that the gap between the model and the implementation can be rigorously quantified leading to predictability if the implementation is viewed as a sequence of control(More)
— We present CSEC (Compositional Symbolic Equivalence Checker), an algorithm and tool to perform automatic and compositional equivalence checking of C code against Simulink models. Such equivalence checking is important in model based development of safety-critical control software in industrial settings, where either the Simulink models are hand-generated(More)
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