Hajo Broersma

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This paper evaluates an algorithm that maps a number of communicating processes to a heterogeneous tiled System on Chip (SoC) architecture at run-time. The mapping algorithm minimizes the total amount of energy consumption, while still providing an adequate Quality of Service (QoS). A realistic example is mapped using this algorithm.
In this note we give an explanation for two phenomena mentioned in the concluding remarks of “The matching polynomial of a polygraph” by Babic et al. The following results are obtained: (1) Although three matrices for given polygraphs defined in the above article in general have different orders, they determine the same recurrence relations for the matching(More)
The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a graph covering algorithm. The graph covering is done in two steps: template generation and template selection. The objective of template generation step is to extract functional equivalent structures, i.e. templates,(More)
Given a graph G = (V,E) and a (not necessarily proper) edgecoloring of G, we consider the complexity of finding a spanning tree of G with as many different colors as possible, and of finding one with as few different colors as possible. We show that the first problem is equivalent to finding a common independent set of maximum cardinality in two matroids,(More)
An asteroidal triple (AT) is a set of three vertices such that there is a path between any pair of them avoiding the closed neighborhood of the third. A graph is called AT-free if it does not have an AT. We show that there is an O(n4) time algorithm to compute the maximum weight of an independent set for AT-free graphs. Furthermore, we obtain O(n4) time(More)