Haider A. F. Almurib

Learn More
This paper proposes three designs of an inexact adder cell for approximate computing. These cells require a substantially smaller number of transistors compared to an exact full adder cell as well as known inexact designs. These inexact cells are simulated at 45 nm and compared with respect to circuit based metrics (such as energy consumption, delay,(More)
This paper presents a Multilevel Phase Change Memory (MLPCM) cell model, the suggested model is MATLAB based and can accurately simulate the behavior of the cell in response to the programming input. The model calculates the resistance of the cell as a function of the crystalline fraction resulting from the temperature generated by the programming current;(More)
This paper details a new coordinated design between power system stabilizers (PSSs) and a unified power flow controller (UPFC) using genetic algorithms (GAs). A GA scheme determines the optimal location for a UPFC while tuning its control parameters, resulting in the optimization of the quantity, parameters, and locations of PSSs under different operating(More)
This paper proposes the use of a novel algorithm for smart direct load control and load shedding to minimize the power outage in sudden grid load changes, as well as reduce the Peak-to-Average Ratio (PAR). The algorithm uses forecasting, shedding, and smart direct load control. The algorithm also uses the Internet of Things and stream analytics to provide(More)
This paper presents a method for operational testing of a memristor-based memory look-up table (LUT). In the proposed method, the deterioration of the memristors (as storage elements of a LUT) is modeled based on the reduction of the resistance range as observed in fabricated devices and recently reported in the technical literature. A quiescent current(More)
This study presents a new method for application testing of field programmable gate array (FPGA) interconnects at run time. This method utilises new features related to the function for the programming of the look up tables (LUTs), the utilisation (by logic activation/deactivation) of the nets in a interconnect configuration as well as the primary (unused)(More)
Research on joint torque reduction in robot manipulators has received considerable attention in recent years. Minimizing the computational complexity of torque optimization and the ability to calculate the magnitude of the joint torque accurately will result in a safe operation without overloading the joint actuators. This paper presents a mechanical design(More)