Hagen Gädke-Lütjens

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We present a low-level infrastructure for use by high-level language to hardware compiler back-ends. It consists of the highly parameterizable, technology-independent module library Modlib and the LMEM framework for localizing variables in fast on-chip memories. Modlib not only supports all high-level language operators (including memory accesses), but also(More)
We present an improved method for scheduling speculative data paths which relies on cancel tokens to undo computations in misspeculated paths. Performancewise, this method is considerably faster than lenient execution, and faster than any other known approach applicable for general (including non-pipelined) computation structures. We present experimental(More)
Control-memory-data flow graphs (CMDFGs) are a unified intermediate representation for compiling high-level languages onto reconfigurable adaptive computing systems. We present both their initial construction as well as transformations for parallel memory accesses. The impact on a number of applications is examined, also considering the effect of caches on(More)
Our concept of a virtual transaction layer (VTL) architecture allows to directly map transaction-level communication channels onto a synthesizable multiprocessor SoC implementation. The VTL is above the physical MPSoC communication architecture, acting as a hardware abstraction layer for both HW and SW components. TLM channels are represented by virtual(More)
Several examples have shown that adaptive computers are capable of outperforming traditional workstations in terms of computing time as well as energy efficiency. Developing applications for an adaptive computer, however, is often a complex task. Hardware (HW) and software (SW) parts as well as their interfaces have to be implemented, requiring specialized(More)
Wavelet-based image compression has been suggested previously as a means to evaluate and compare both traditional and reconfigurable computers in terms of performance and resource requirements. We present a reconfigurable implementation of such an application that not only achieves a performance comparable to that of recent CPUs, but does so at a fraction(More)
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