Hafijur Rahman

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Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage mechanism of such circuits is the gate leakage. This paper first describes a fast leakage estimation technique based on biasing states for both gate leakage and sub-threshold leakage. Next, it describes a leakage reduction method based on the(More)
Timing information in the form of clock or oscillator signals play a critical role in most modern applications. The timing jitter or uncertainty in the timing information presents a serious limitation in the achievable system performance. For instance, timing errors can degrade the signal-to-noise ratio (SNR) of an A/D converter, limit the speed of a(More)
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