Hae-woo Park

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With the continuous scaling of semiconductor technology, the life-time of circuit is decreasing so that processor failure becomes an important issue in MPSoC design. A software solution to tolerate run-time processor failure is to migrate tasks from the failed processors to the live processors when failure occurs. Previous works on run-time task migration(More)
Embedded software design for a multicore platform involves parallel programming for heterogeneous multiprocessors with diverse communication architectures under design constraints such as hardware cost, power, and timeliness. Since the classical von Neumann programming model assumes sequential execution of programs, it is not adequate for MPSoC SW(More)
Extensive work has been done for optimal management of scratch-pad memory (SPM) all assuming that the SPM is assigned a fixed address space. The main target objects to be placed on the SPM have been code and global memory since their sizes and locations are not changed dynamically. We propose a novel idea of dynamic address mapping of SPM with the(More)
A target independent specification model, called CIC (Common Intermediate Code) has been proposed to specify an application in a fashion that all potential functional and data parallelism are explicitly defined by the programmer. After mapping of an application to the target processors it is performed to exploit the parallelism optimally, the CIC translator(More)
In this paper we propose a dynamic code overlay technique of synchronous data-flow (SDF)-modeled program for low-end embedded systems which lack MMU-support. With this technique, the system can utilize expensive SRAM memory more efficiently by using flash memory as code storage. SRAM is divided into several regions called overlay slots. A data-flow block or(More)
Actor model-based design is actively researched for parallel embedded SW design since the model exposes the potential parallelism explicitly in an architecture-neutral form. In most actor-oriented models, actors are self-contained and data channels are the only sharable object between actors, and they compose a system in a flat layer. In contrast, it is(More)
Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to keep memory consistency from simultaneous accesses of both ports, every access to the shared memory should be(More)
With the continuous scaling of semiconductor technology, failure rate is increasing significantly so that reliability becomes an important issue in multiprocessor System-on-Chip (MPSoC) design. We propose an optimal checkpoint selection with task duplication hardening to tolerate transient faults. A target application is specified in a task graph, and the(More)
Since the design validation and correction cost is drastically increasing as the design steps proceed, software verification is considerably desired before the simulation model for the target architecture is constructed. As timing correctness is as important as functional correctness in real-time multimedia embedded systems, an important research issue is(More)
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