The architecture and its implementation ofAbsm~-PIPE (Parallel Instructions and Pipelined Execution) is a research vehicle for high performance VLSI architectures and organizations and makes extensive use of architectural queues.
This analysis suggests that the TPC benchmarks tend to exercise the following aspects of the system differently than the production workloads: concurrency control mechanism, workload-adaptive techniques, scheduling and resource allocation policies, and I/O optimizations for temporary and index files.
This paper derives an analytical model for the execution of a pipeline segment, and develops heuristic schemes to determine the query execution plan based on a segmented right-deep tree so that the query can be efficiently executed.
A comprehensive analysis of the logical I/O reference behavior of the peak productiondatabase workloads from ten of the world's largest corporations, focusing on how these workloads respond to different techniques for caching, prefetching, and write buffering.
It is demonstrated that ALIS considerably outperforms prior techniques, improving the average read performance by up to 50% for server workloads and by about 15% for personal computer workloads, and that the performance improvement persists as disk technology evolves.
It is claimed that SFR improves the worst-case cost for a distributed join, but it will not displace specialized distributed join algorithms when the later are applicable.
This paper introduces a new technique which is flexible, and performs well for general queries, which is proposed to address the problems of multidimensional data declustering in shared-nothing parallel database systems.
Experimental results show that, while dynamic programming produces the be& plans, simple heuristics often do nearly as well as dynamic programming, and the advantages of bushy execution trees over more restricted tree shapes are highlighted.
This work proposes a novel algorithm that exhibits complete parallelism during the sort, merge, and return-tohost phases, and decreases the amou@ of inter-processor communication compared to existing parallel sort algorithms.
A general smart storage (SmartSTOR) architecture in which a processing unit that is coupled to one or more disks can be used to perform off-loaded processing, and suggests that there is a definite performance advantage in using fewer but more powerful processors.