H. Wong

Publications354
h-index34
Citations4,056
Highly Influential Citations60
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On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors
Approximation of the length of velocity saturation region in MOSFET's
This work presents an accurate approximation of the length of velocity saturation region (LVSR) based on the calculation of one-dimensional (1-D) electric field distribution near the drain region of…
A physically-based MOS transistor avalanche breakdown model
A physically based breakdown model for MOSFET's is presented to rectify the unexplained experimental breakdown behaviors. The drain avalanche breakdown in the MOS transistor can be caused by either…
A novel gate boosting circuit for 2-phase high voltage CMOS charge pump
A novel gate boosting circuit is proposed for general switched-capacitor charge pump. The proposed circuit only requires two small transistors to generate the necessary driving signal from a clock…
Electronic structure of α-Al2O3: Ab initio simulations and comparison with experiment
Al2O3 films 150 Å thick are deposited on silicon by the ALD technique, and their x-ray (XPS) and ultraviolet (UPS) photoelectron spectra of the valence band are investigated. The electronic band…
Atomic and electronic structure of amorphous and crystalline hafnium oxide: X-ray photoelectron spectroscopy and density functional calculations
The atomic structure of amorphous and crystalline hafnium oxide (HfO2) films was examined using x-ray diffractometry and Hf edge x-ray absorption spectroscopy. According to the x-ray photoelectron…
Analytical model of drain current of cylindrical surrounding gate p-n-i-n TFET
Robust and area-efficient nLDMOS-SCR with waffle layout structure for high-voltage ESD protection
A novel waffle-type nLDMOS-SCR ESD clamp with compact source and drain for high-voltage ESD protection is proposed and realised using the 0.35 µm, 30/5 V bipolar-CMOS-DMOS (BCD) process. With this…
Double edge-triggered half-static clock-gated D-type flip-flop
This paper proposes a double edge-triggered half-static clock-gated D-type flip-flop (DHSCGFF), which consists of two parallel dynamic master latches connected in parallel and a single half-static…
Study of the electronic trap distribution at the SiO/sub 2/-Si interface utilizing the low-frequency noise measurement
A correlation of the trap distribution at the silicon-oxide interface with the low-frequency noise measurement in MOS devices at temperatures ranging from 77 to 300 K is presented. Several devices…
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