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Distributed Processing Applications for UAV/drones: A Survey
TLDR
This paper surveys the applications implemented over cooperative teams of UAVs that operate as distributed processing systems and the distributed processing system principles.
Brain MRI Slices Classification Using Least Squares Support Vector Machine
TLDR
Advanced classification techniques based on Least Squares Support Vector Machines (LS-SVM) are proposed and applied to brain image slices classification using features derived from slices and compared with other classifiers like SVM with linear and nonlinear RBF kernels, RBF classifier, Multi Layer Perceptron (MLP) classifier and K-NN classifier.
A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis
TLDR
An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function and is suitable for different types of FPGAs including XILINX, ACTEL and ALGOTRONIX devices.
An application of functional decomposition in ROM-based FSM implementation in FPGA devices
A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing
TLDR
A survey of HLLs, tools, andCompilers used for translating high level representation to hardware description language is presented and technical analysis of such tools and compilers is discussed as well.
Content based image retrieval using a neuro-fuzzy technique
TLDR
A neuro-fuzzy technique for content based image retrieval based on fuzzy interpretation of natural language, neural network learning and searching algorithms that can be used for any real-world online database.
Balanced multilevel decomposition and its applications in FPGA-based synthesis
TLDR
A general decomposition concept is presented and the results prove that the method is efficient and does not suffer from its generality.
Fast FPGA-based fault injection tool for embedded processors
TLDR
This paper solves the area overhead problem related with observation data in fault injection experiments by bringing all parts of fault injection tool inside FPGA and using simple observation circuit.
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