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Device scaling limits of Si MOSFETs and their application dependencies
This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of theExpand
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CMOS scaling into the nanometer regime
Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light ofExpand
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Technology and device scaling considerations for CMOS imagers
This paper presents an analysis of the impact of device and technology scaling on active pixel CMOS image sensors. Using the SLA roadmap as a guideline, we calculate the device characteristics thatExpand
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Nanoscale CMOS
This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, weExpand
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Extension and source/drain design for high-performance FinFET devices
Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. AngledExpand
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Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 /spl mu/m MOSFET's
  • H. P. Wong, Y. Taur
  • Materials Science
  • Proceedings of IEEE International Electron…
  • 5 December 1993
In this paper, discrete random dopant distribution effects in sub-0.1 /spl mu/m MOSFET's were studied using three-dimensional drift-diffusion "atomistic" simulations. Effects due to the randomExpand
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Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs
  • K. Rim, J. Chu, +16 authors H. P. Wong
  • Materials Science
  • Symposium on VLSI Technology. Digest of Technical…
  • 11 June 2002
Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltageExpand
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A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification
A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. Expand
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A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements
We present a data-calibrated compact model of carbon nanotube (CNT) FETs (CNTFETs) based on the virtual-source (VS) approach, describing the intrinsic current-voltage and charge-voltageExpand
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A CMOS-integrated 'ISFET-operational amplifier' chemical sensor employing differential sensing
The ISFET (ion-sensitive field-effect transistor) pH sensor is first matched with a MOSFET at the differential input stage of a CMOS operational amplifier (called the ISFET-operational amplifier) toExpand
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