• Publications
  • Influence
Introduction to the Cell multiprocessor
This paper provides an introductory overview of the Cell multiprocessor. Cell represents a revolutionary extension of conventional microprocessor architecture and organization. The paper discussesExpand
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Synergistic Processing in Cell's Multicore Architecture
Eight synergistic processor units enable the Cell Broadband Engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar andExpand
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Power efficient processor architecture and the cell processor
  • H. P. Hofstee
  • Computer Science
  • 11th International Symposium on High-Performance…
  • 12 February 2005
This paper provides a background and rationale for some of the architecture and design decisions in the cell processor, a processor optimized for compute-intensive and broadband rich mediaExpand
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Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI
This paper describes the architecture and implementation of the original gaming-oriented synergistic processor element (SPE) in both 90-nm and 65-nm silicon-on-insulator (SOI) technology andExpand
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True hardware random number generation implemented in the 32-nm SOI POWER7+ processor
This paper provides a description of the hardware random number generator that is implemented on the IBM POWER7+™ processor. We discuss the underlying mechanism using basic ring oscillator circuitsExpand
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Designing for a gigahertz [guTS integer processor]
At the IEEE International Solid State Circuits Conference this February, the IBM Austin Research Laboratory presented an experimental 64-bit integer processor called guTS (gigahertz unit Test Site).Expand
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ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator
In this paper, we propose ExtraV, a framework for near-storage graph processing. It is based on the novel concept of graph virtualization, which efficiently utilizes a cache-coherent hardwareExpand
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The design methodology and implementation of a first-generation CELL processor: a multi-core SoC
This paper reviews the design challenges that current and future processors must face with stringent power limits and high frequency targets, and the design methods required to address the continuingExpand
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Verification of delayed-reset domino circuits using ATACS
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austin Research Laboratory.Expand
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Understanding system design for Big Data workloads
This paper explores the design and optimization implications for systems targeted at Big Data workloads. We confirm that these workloads differ from workloads typically run on more traditionalExpand
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