• Publications
  • Influence
Circuit analysis and optimization driven by worst-case distances
In this paper, a new methodology for integrated circuit design considering the inevitable manufacturing and operating tolerances is presented. It is based on a new concept for specification analysisExpand
  • 192
  • 7
The sizing rules method for analog integrated circuit design
Presents the sizing rules method for analog CMOS circuit design that consists of: first, the development of a hierarchical library of transistor pair groups as basic building blocks for analog CMOSExpand
  • 131
  • 6
  • Open Access
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis
This paper presents the sizing rules method for basic building blocks in analog CMOS and bipolar circuit design. It consists of the development of a hierarchical library of transistor-pair groups asExpand
  • 120
  • 6
Performance trade-off analysis of analog circuits by normal-boundary intersection
We present a new technique to examine the trade-off regions of a circuit where its competing performances become "simultaneously optimal", i.e. Pareto optimal. It is based on circuit simulation,Expand
  • 62
  • 4
  • Open Access
A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems
This work focuses on the generation of the Pareto front for practical applications such as analog circuit sizing. The Pareto front is the solution to a multiobjective optimization problem. It showsExpand
  • 84
  • 4
Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier–Motzkin Elimination
This paper presents two simulation-based methods for the calculation of the feasible performance values of analog integrated circuits. The first method computes the Pareto-optimal tradeoffs ofExpand
  • 57
  • 4
A CPPLL hierarchical optimization methodology considering jitter, power and locking time
In this paper, a hierarchical optimization methodology for charge pump phase-locked loops (CPPLLs) is proposed. It has the following features: 1) A comprehensive and efficient behavioral modeling ofExpand
  • 37
  • 4
  • Open Access
Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions
The analog placement algorithm Plantage, presented in this paper, generates placements for analog circuits with comprehensive placement constraints. Plantage is based on a hierarchically boundedExpand
  • 30
  • 2
  • Open Access
Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits
This paper presents a new method to automatically generate hierarchical placement rules, which are crucial for a successful analog placement. The method is based on a novel symmetry computationExpand
  • 34
  • 2
Mismatch analysis and direct yield optimization by specwise linearization and feasibility-guided search
We present a new method for mismatch analysis and automatic yield optimization of analog integrated circuits with respect to global, local and operational tolerances. Effectiveness and efficiency ofExpand
  • 45
  • 1
  • Open Access