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A 10 GHz reconfigurable CMOS LNA for UWB receiver is presented. The LNA is fabricated with the 0.13 mum standard CMOS process. Measurement of the chip is performed on a ADS simulator. In the UWB… (More)
In this paper a digital UWB transceiver is designed with a bit-rate of 200 Mb/s. System simulations propose an SNR of 10 dB, and 4-bit of resolution with 4 GHz sampling rate for analog to digital… (More)
High speed electronic systems demand frequency synthesizer of high resolution, wide bandwidth and fast switching speed. The "Flying-Adder" architecture is a frequency and phase synthesis technique… (More)
IDS is a protective system which identifies the occurring violations on the network and its performance is based on different methods. The most common method of IDS performance relies on patter… (More)
We try to optimize the fully integrated phase path for a 3G polar transmitter in deep sub micron CMOS. It includes a single quad band digitally controlled oscillator (DCO) providing modulation… (More)