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Anomalous C-V characteristics of implanted poly MOS structure in n/sup +//p/sup +/ dual-gate CMOS technology
The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristicsExpand
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Polysilicon encapsulated local oxidation
Polysilicon encapsulated local oxidation (PELOX) is proposed as an effective isolation technique that satisfied advanced device requirements without any difficult-to-control structures or processes.Expand
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A high-performance quadruple well, quadruple poly BiCMOS process for fast 16 Mb SRAMs
An advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts,Expand
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Technology for the fabrication of A 1 MB CMOS DRAM
We describe the cell structure and fabrication methods employed for a practical 1 MB CMOS DRAM. This process combines concentrated efforts in the cell array with a core technology of 1.25 uM Twin-TubExpand
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Recessed polysilicon encapsulated local oxidation
Local oxidation of silicon (LOCOS) is the most commonly used isolation technology in silicon integrated circuits. The inherently large field oxide encroachment associated with LOCOS severely limitsExpand
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A high-performance low-complexity bipolar technology using selective collector compensation
This paper describes a novel bipolar technology which achieves very high ECL performance while maintaining low process complexity, large fabrication tolerances, and full CMOS compatibility. The highExpand
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