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Synthesis of full-adder circuit using reversible logic
TLDR
This paper introduces a reversible full-adder circuit that requires only three reversible gates and produces least number of "garbage outputs ", that is two. Expand
Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder
  • H. Babu, A. Chowdhury
  • Mathematics, Computer Science
  • 18th International Conference on VLSI Design held…
  • 3 January 2005
TLDR
In this paper, we have proposed a design technique for the reversible circuit of binary coded decimal (BCD) adder that poses all the good features of reversible logic synthesis. Expand
Efficient approaches for designing reversible Binary Coded Decimal adders
TLDR
This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. Expand
An Efficient Design of a Reversible Barrel Shifter
  • Irina Hashmi, H. Babu
  • Computer Science
  • 23rd International Conference on VLSI Design
  • 3 January 2010
TLDR
The key objective of today’s circuit design is to increase the performance without the proportional increase in power consumption. Expand
Reversible logic synthesis for minimization of full-adder circuit
TLDR
This paper introduces an approach to synthesise the generalized multi-rail reversible cascades and minimizing the "garbage bit" and number of reversible gates, which is the main challenge of reversible logic synthesis. Expand
Design of a compact reversible binary coded decimal adder circuit
TLDR
We propose a new reversible circuit named as reversible binary coded decimal (BCD) adder, which is the first ever proposed in reversible logic synthesis. Expand
Cost-efficient design of a quantum multiplier–accumulator unit
  • H. Babu
  • Mathematics, Computer Science
  • Quantum Inf. Process.
  • 2017
TLDR
We propose a cost-efficient quantum multiplier–accumulator unit, which performs better than the existing ones in terms of depth, quantum gates, delays, area and power with the increasing number of qubits. Expand
A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors
TLDR
In this paper, we presented the design methodologies of an n-to-2n reversible fault tolerant decoder, where n is the number of data bits. Expand
A new approach to synthesize multiple-output functions using reversible programmable logic array
TLDR
In this paper, we propose a completely regular structure for realizing Boolean functions, namely Reversible Programmable Logic Array (RPLA). Expand
Efficient approaches to design a reversible floating point divider
  • Lafifa Jamal, H. Babu
  • Mathematics, Computer Science
  • IEEE International Symposium on Circuits and…
  • 19 May 2013
TLDR
We propose a reversible n-bit divider, where n is the number of bits of the operands of dividend. Expand
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