This paper introduces a reversible full-adder circuit that requires only three reversible gates and produces least number of "garbage outputs ", that is two.Expand

18th International Conference on VLSI Design held…

3 January 2005

TLDR

In this paper, we have proposed a design technique for the reversible circuit of binary coded decimal (BCD) adder that poses all the good features of reversible logic synthesis.Expand

This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder.Expand

This paper introduces an approach to synthesise the generalized multi-rail reversible cascades and minimizing the "garbage bit" and number of reversible gates, which is the main challenge of reversible logic synthesis.Expand

We propose a new reversible circuit named as reversible binary coded decimal (BCD) adder, which is the first ever proposed in reversible logic synthesis.Expand

We propose a cost-efficient quantum multiplier–accumulator unit, which performs better than the existing ones in terms of depth, quantum gates, delays, area and power with the increasing number of qubits.Expand