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We demonstrate a dynamic Verilog-A RRAM compact model capable of simulating real-time DC cycling and pulsed operation device behavior, including random variability that is inherent to RRAM. This paper illustrates the physics and capabilities of the model. The model is verified using different sets of experimental data. The DC/Pulse parameter fitting(More)
A novel vertical RRAM for 3D cross-point architecture is proposed. The design and optimization issues of the proposed vertical RRAM for 3D cross-point architecture array are addressed from both device and array levels. A double layer stacked HfO<sub>x</sub> based vertical RRAM devices with interface engineering fabricated using a cost-effective fabrication(More)
Fig. 5. Scaling capability of DG MOSFETs. (a) Design contours of a 15-nm undoped DG MOSFETs for different requirements. (b) Projections of minimum channel length as a function of silicon thickness (is assumed to be 0.8 nm). (t ox is assumed to be 0.8 nm). Clearly, 10 nm undoped DG MOS-FETs are likely to find their first applications in places where S = 100(More)
High mobility III&#x2013;V compounds is a strong contender for extending high performance logic beyond the 22 nm technology node [1&#x2013;3]. However, demonstrations of exceptional III&#x2013;V performance required device footprints on the &#x00B5;m-scale despite nm-scale gate lengths, in order to avoid source/drain shorting during contact alloying. The(More)
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