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In this study, a novel model called Function Deployment Model (FDM) for decision making in new product development is introduced. To demonstrate its usefulness pragmatically, the model is applied to the design problem of development of the micro/nano injection molding machine. Based on the Quality Function Deployment (QFD) technique, this model translates(More)
As semiconductor technology advance, NVM memory structure find more and more application in the IC product. Majority part of NVM is charge-based where charge can be injected into or removed from a critical region of a device. This storage cell is normally floating and cannot be accessed directly. So the analysis on this floating structure is quite(More)
As the technology keep scaling down and IC design becoming more and more complex, failure analysis becomes more and more challenge, especially for static laser analysis. For the foundry FA or process monitoring, SRAM analysis becomes more and more critical. There are two reasons for this: The first one is that SRAM circuit is relative simple which is well(More)
Several lots suffer from electrical monitor structure fail, which failed the wafer center contact chain high resistance. EFA was performed on the failed unit. Compared with good unit, high resistance contact chain was found by I-V curve tracing, but the high resistance curve is a non-linear I-V curve. TIVA was employed to do electrical fault isolation and(More)
As the semiconductor technology keeps scaling down, Poly silicon gate pattern becomes more and more critical. If the Poly silicon variation is too big or some mismatch, it will induce severe logic parametric fail or even functional fail, which is difficult for the failure analysis. For the analog device, it ca n induce functional fail. In this case, a(More)
Conventional die soak in hydrofluoric acid (HF) to prepare SIMS sample for gate oxide depth profiling analysis works well for large-size poly-Si pattern. However, for small-size poly-Si pattern (<; 50μm), the HF soak results in abnormality in the SIMS depth profiling. A mechanical polish combined with HF soak was proposed to solve the problem.
Wafer Level Chip Scale Packaging (WLCSP) involves more bumping process steps after receiving the passivated product wafer from the foundry manufacturing line. As wafer sort is usually tested after the bumping process, on the solder bump, any process drift during bumping, especially the contact resistance degradation at the Aluminum (Al) pad to(More)
This paper demonstrates a new de-process flow for MEMS resonator DRG (dc Resistance to Ground) failure analysis, using electrical fault isolation tool of TTVA to locate the defect site. After all, cutting method was performed to de-process MEMS from Si Cap, followed by SEM inspection to successfully observe the physical defect point. Auger analysis was then(More)
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