H. Herman M. Pang

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A low-jitter charge-pump PLL is built in 90-nm CMOS for 1–10 Gb/s SerDes transmitter clocking. The PLL employs a programma-ble dual-path loop filter with integrating path and novel resistorless proportional path that can be independently controlled and accurately modeled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized(More)
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