H. Fatih Ugurdag

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We present a new parallel, adaptable algorithm, which plays Mastermind game, and its FPGA implementation. The proposed algorithm is a cross between Shapiro's, Knuth's, and Kooi's algorithms, has low-computational complexity but still offers competitive game results. The FPGA design part required subtle architectural decisions and trade-off between area,(More)
Nanocrossbars (i.e., nanowire crossbars) offer extreme logic densities but come with very high defect rates; stuck-open/closed, broken nanowires. Achieving reasonable yield and utilization requires logic mapping that is defect-aware even at the crosspoint level. Such logic mapping works with a defect map per each manufactured chip. The problem can be(More)
Anti-dependencies are a major cause of bottleneck in software pipelining. Anti-dependencies can be removed in software by code duplication as in the technique of modulo variable expansion. However, it is possible to eliminate anti-dependencies in hardware. So far, two such VLIW architectures have been proposed: Poly-cyclic and URPR-1 architectures. These(More)
Dynamic Partial Reconfiguration (DPR) of Xilinx FPGAs in cases where there is significant logic difference between subsequent configurations is made possible by Xilinx module-based PR flow. Xilinx supports this flow only for high-end FPGAs and requires paid license, without which Xilinx PlanAhead software disables the related knobs and features. This poster(More)