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This paper describes and analyzes a low noise and high bandwidth transimpedance amplifier featuring a large dynamic range. The designed amplifier is configured on three identical stages that use an active load compensated by an active resistor to improve the stability performance of the amplifier. This topology displays a transimpedance gain of 150k/spl(More)
In this paper, a low noise and high bandwidth transimpedance amplifier (TIA) is designed for optical receiver using a 0.18 μm standard in CMOS technology. The proposed circuit operates at a data rate of 13.25 Gb/s. Employing a series inductive peaking technique, an improvement of bandwidth by only one inductor within the structure is achieved to(More)
This paper presents a low noise and high bandwidth transimpedance amplifier (TIA) for optical receiver, operating at data rate of 10 Gb/s. The first configuration of the amplifier which is the basic structure is based on push-pull inverter with resistor in feedback. However, the second configuration employs an inductor in series with a resistor in the(More)
This paper presents a transimpedance amplifier for photoreceiver circuit. The proposed structure operates at a data rate of 10 Gb/s at a BER of 10<sup>-12</sup> and was implemented in a 0.18 &#x03BC;m CMOS process. The structure achieves a wide bandwidth (6.3 GHz). We used NMOS transistors as active resistor to increase bandwidth and to reduce noise level.(More)
This work describes how feed-forward Artificial Neural Networks (ANNs) can perform Analog-to-Digital (A/D) conversion with a linear and non-linear relationship between the analog input and the digital output in order to eliminate the linearization stage without modifying the analog-to-digital converter's elements and architecture. Adding to that, the speed(More)
This paper presents an integrated optical receiver which consists of an integrated photodetector, and a transimpedance circuit. A series inductive peaking is used for enhancing the bandwidth. The proposed structure operates at a data rate of 10 Gb/s with a BER of 10 and was implemented in a 0.35 μm CMOS process. The integrated photodiode has a capacitance(More)
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