H. C. Campos Neto

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In this paper, we describe a modular reconfigurable architecture for efficient stuck-at fault simulation in digital circuits. The architecture is based on a Universal Faulty Gate Block, which models each 2-input gate by a 4-input Look-Up Table (LUT) and a Shift-Register (SR) with 3 stages, and relies on colapsing the stuck-at fault list of the gates using(More)
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