Gyu-Seob Jeong

  • Citations Per Year
Learn More
This paper describes a CMOS interface circuit for silicon photonics. 20-Gb/s operation of an optical receiver frontend circuit is demonstrated using an optical signal applied to the optical front-end. The transimpedance amplifier (TIA) is based on an inverter with resistive and inductive feedback for low power consumption and frequency compensation. A(More)
We present the hybrid-integrated silicon photonic receiver and transmitter based on silicon photonic devices and 65 nm bulk CMOS interface circuits operating over 30 Gb/s with a 10(-12) bit error rate (BER) for λ ~1550nm. The silicon photonic receiver, operating up to 36 Gb/s, is based on a vertical-illumination type Ge-on-Si photodetector (Ge PD)(More)
An all-digital spread spectrum clock generator (SSCG) using two-point modulation is presented. To calibrate the gain mismatch between two modulation paths, a background gain calibration method is proposed. To reduce power consumption and design complexity, the bang-bang phase-frequency detector (BBPFD) is used instead of the time-to-digital converter (TDC).(More)