Gyu-Hyun Kim

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For the first time, this paper presents the results of successful integrations of Cu wiring into a production 512 Mb/90 nm design-rule stacked capacitor and recessed gate DDR (double data rate) DRAM technology, focusing on the effects of Cu integration on DRAM performance, yield, refresh time, and wafer-level reliability. 2 levels Cu interconnect (Ml single(More)
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