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This paper discusses the implementation details and silicon result of a 1.6 GHz dual-core Cortex-A9 on a low power High-K Metal Gate 32nm CMOS Bulk Process [1]. The implementation is based on a fully synthesizable flow utilizing ARM Standard Cell and Memory IP. The completed design includes power gating and Dynamic Voltage Frequency Scaling capabilities for(More)
Dynamic power is a keenly analysed design parameter in SRAM memory design especially in low power battery operated systems. A simple way to reduce dynamic power (and leakage power) is to lower the operating voltage to the minimum possible for a given operating speed requirement. The transistor threshold voltages ultimately define the lowest operating(More)
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