Gurshaant Singh Malik

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This paper presents a new hierarchical architecture for parallelizing the computation intensive rapidly exploring random tree problem. The architecture resembles a tree like structure that agglutinates minimal inter-module communication of a shared memory with data integrity of a distributed memory. Another novelty of this research has been in(More)
— Field Programmable Gate Arrays(FPGA) exceed the computing power of software based implementations by breaking the paradigm of sequential execution and accomplishing more per clock cycle by enabling hardware level parallelization at an architectural level. Introducing parallel architectures for a computationally intensive algorithm like Rapidly Exploring(More)
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