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Future neutrino physics experiments intend to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. To increase performance, integrated readout electronics should work inside the cryostat. Due to the scale and cost associated with evacuating and filling the cryostat, the electronics will be unserviceable for(More)
A novel low-power low-jitter 25 Gb/s clock and data recovery (CDR) circuit with equalizer that can work at an ultra-low supply voltage of 0.6 V is proposed and implemented in a 65 nm CMOS process. A two-tank transformer-feedback technique is proposed in the 25 GHz LC-tank VCO to improve the phase noise performance at low supply voltage. Forward-body biasing(More)
The Deep Underground Neutrino Experiment will use unsurpassed quantities of liquid argon to fill a time projection chamber. Research is under way to place the electronics inside the cryostat. For reasons of efficiency and economics, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET(More)
A low-voltage, two-stage ring voltage-controlled oscillator (VCO) which can tolerate temperature variation is presented in this paper. Designed using a 0.13 μm CMOS technology, this VCO is capable of operating at 1-V power supply voltage not only for low power consumption, but also to reduce hot-carrier effects and improve reliability and lifetime.(More)
This paper presents a low-power 28 Gb/s PLL-based clock and data recovery circuit in 65 nm CMOS technology. The artificial LC transmission line technique is proposed to be used in the full-rate bang-bang phase detector to reduce the number of D-latches and save power consumption by 42.8% compared with the conventional phase detector design. By using the(More)
An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new low-power two-step PI (TSPI) with high linearity over 4-8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase(More)
Based on test results and a procedure that can isolate threshold voltage degradation and mobility degradation from drain current degradation, we found that the log-log curves of mobility degradation show saturation with a change of slope from about 0.4 to smaller values at room temperature. Although both the mobility and threshold voltage degradations are(More)
This paper presents a low-power 10-Gb/s vertical cavity surface emitting laser (VCSEL) driver integrated circuit (IC) with electrostatic discharge (ESD) protection in the 130-nm CMOS technology. A distributed amplifier (DA)-based modulator is proposed to boost the driver bandwidth. It employs artificial transmission lines to cancel the device parasitic(More)
A novel triple-path PLL (TPPLL) is presented to compensate the VCO frequency drift caused by the large temperature variations meanwhile maintaining a stable bandwidth and good jitter performance. The proposed PLL architecture splits the VCO tuning loop into three paths as the proportional, the integral, and the temperature compensation (TC) path,(More)