Learn More
This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single-input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences. The proposed(More)
A novel approximation of 2-D potential function perpendicular to the channel for fully depleted (FD) silicon-on-insulator (SOI) MOSFETs on films with vertical Gaussian profile is proposed in the paper, then an analytical threshold voltage model is derived. The model agrees well with the MEDICI numerical simulation results. It represents a feasible way to(More)
This paper presents an improved latched comparator which is suitable for high speed folding and interpolation ADC. The proposed comparator minimizes the kick back noise. Dummy transistors are introduced in the switch circuit to suppress clock feedthrough. Transistors in common-gate arrangement are inserted to reduce kick back noise. Simulated result of the(More)
A programmable low-frequency filter for biomedical signal sensing application is presented here based on the principle of fifth-order Bessel transconductance capacitor (Gm-C) ladder filter. Current division and current cancellation techniques are used to achieve ultra-low Gm for operation transconductance amplifier (OTA) design. Active inductor is designed(More)
Model parameter extraction plays an important role in bridging semiconductor manufacturing and integrated circuit design. Most commercial extraction and optimization tools have a default extraction and optimization procedure. PSO (Particle Swarm Optimization) is a global random searching algorithm with swarm intelligence, having the strong searching(More)
The impact of gate voltage differences on the performance of the novel n-type silicon homojunction SOI-Tunnel FET is studied. Based on numerical simulation results using Synopsys Technology Computer-Aided Design (TCAD), the higher on-current and the ultra-low off-current are observed as compared to that of a conventional SOI-Tunnel FET. The analysis of(More)
Fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs have attracted considerable attention due to their superior short-channel immunity and ideal subthreshold characteristics. With the size of device scaling down, the subthreshold operation has become an important area in integrated circuits design nowadays. A number of theoretical models accounting for(More)