Guido Groeseneken

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The similarity between Random Telegraph Noise and Negative Bias Temperature Instability (NBTI) relaxation is further demonstrated by the observation of exponentially-distributed threshold voltage shifts corresponding to single-carrier discharges in NBTI transients in deeply scaled pFETs. A SPICE-based simplified channel percolation model is devised to(More)
With further scaling of nanometer CMOS technologies, yield and reliability become an increasing challenge. This paper reviews the most important phenomena affecting yield and reliability. For each effect, the basic physical mechanisms causing the effect and its impact on transistor parameters are described. Possible solutions to cope/handle with these(More)
A blueprint for an atomistic approach to introducing time-dependent variability into a circuit simulator in a realistic manner is demonstrated. The approach is based on previously proven physics of stochastic properties of individual gate oxide defects and their impact on FET operation. The proposed framework is capable of following defects with widely(More)
The ubiquity of threshold voltage relaxation is demonstrated in samples with both conventional and high-k dielectrics following various stress conditions. A technique based on recording short traces of relaxation during each measurement phase of a standard measure-stress-measure sequence allows monitoring and correcting for the otherwise-unknown relaxation(More)
The tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at nanometer dimensions. In general, the TFET current can be decomposed into two components referred to as point tunneling and line tunneling. In this paper we derive a compact analytical model for the current due to point tunneling complementing the(More)
Despite a number of recent advances made in understanding bias temperature instability (BTI), there is still no simple simulation methodology available which can capture the impact of BTI degradation on deeply scaled transistors, while incorporating the widely distributed defect parameters. We present a physics-based defect-controlled methodology for(More)
Although only a few defects will be present in the gate dielectric of deeply-downscaled CMOS devices, their relative impact may become intolerable [1]. An individual charged defect can significantly alter the channel current ID of a nm-sized FET, causing VTH fluctuations (RTN) and time dependent VTH variability. Based on detailed understanding of atomistic(More)
Broad similarity between negative bias temperature instability (NBTI) relaxation and 1/f noise is observed. Individual transitions in NBTI relaxation in small pFETs are observed and Poisson defect number statistics is inferred. Finally, it is argued that the wide distribution of defect times should be considered in addition to defect number variation in(More)
We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different technologies, based on which we propose a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on the electrical characteristic of deeply scaled transistors. Among the considered technologies, nanoscaled SiGe channel devices show(More)
6Å EOT Si0.45Ge0.55 pFETs with 10 year lifetime at operating conditions (VDD=1V) are demonstrated. Ultra-thin EOT is achieved by interfacial layer (IL) scavenging. Negative Bias Temperature Instability (NBTI) is alleviated using a high Ge fraction, a thick SiGe quantum well (QW) and a thin Si cap. Hot Carrier Injection (HCI) and Time Dependent Dielectric(More)