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A 1.2 V 12-bit 150 MS/s pipelined ADC with low-gain op-amps (DC gain ≈15 dB) is fabricated in a 65-nm CMOS process. The proposed 5-transistor single stage op-amp enables simple analog circuit to achieve low power and high speed. Digital background calibration technique is exploited to compensate the inter-stage gain error, capacitor mismatch and(More)
This paper presents an improved DC-offset cancellation (DCOC) circuit for programmable-gain amplifier (PGA) in power line communication. It is a speed-enhanced and low-noisy method by using current-mode feedback. The output DC-offset can be reduced from several hundred millivolts to less than 5mV over 64 dB gain range. Furthermore, this proposed technique(More)
The nanoscale origins of ferroelastic domain wall motion in ferroelectric multilayer thin films that lead to giant electromechanical responses are investigated. We present direct evidence for complex underpinning factors that result in ferroelastic domain wall mobility using a combination of atomic-level aberration corrected scanning transmission electron(More)
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