Guangyin Feng

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This work presents a parallel direct-conversion and double-conversion transceiver to solve the problems of crosstalk and LO pulling in the carrier aggregation scenario. An EVM of -34.9 dB is obtained when the output power of the PA driver is 0.4 dBm. Three aggregated carriers with 80 MHz 256-QAM modulation are demonstrated. To the authors' best knowledge,(More)
Future data-oriented computing requires intensive memory access with burden of I/O interconnection. Traditional wired interconnect has limited bandwidth and energy-efficiency with no feature of configurability. This paper introduces an adaptive sub-THz wireless interconnect between cores and main memory (DRAMs) using MIMO beamforming. To satisfy the(More)
Free-space EM-wave based GHz interconnect suffering significant loss and narrow bandwidth cannot be deployed as low-power and dense I/Os for future network-on-chip (NoC) integration of many-core and memory. This paper proposes an energy-efficient and low-crosstalk sub-THz (0.1T-1T) I/O using surface-plasmonic based interconnects and oscillator in CMOS. By(More)
A fully integrated 93.4-to-104.8 GHz 57 mW cascaded PLL, with true in-phase injection-coupled QVCO, occupies 0.88 mm<sup>2</sup> in 65 nm CMOS. By cascading the fractional-N PLL and the sub-sampling PLL, good phase noise, high resolution and wide acquisition range are achieved simultaneously. The measured phase noise of QVCO and PLL are -112.67 and -108.75(More)
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