Gregory W. Donohoe

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The objective of this work is to demonstrate the use of reconfigurable computing for on-board automatic processing of remote sensing data. The Field Programmable Processor Array (FPPA), a radiation tolerant alternative to Field Programmable Gate Arrays, developed at NASA/Goddard under ESTO funding, is the computation engine of our study, while preliminary(More)
OBJECTIVE Psychotic symptoms are common in the population and index risk for a range of severe psychopathological outcomes. We wished to investigate functional connectivity in a community sample of adolescents who reported psychotic symptoms (the extended psychosis phenotype). METHOD This study investigated intrinsic functional connectivity (iFC) during(More)
The development of a practical magnetic tunneling junction (MTJ) ten years ago allowed the creation of a new class of non-volatile memories. This technology may offer superior resistance to total ionizing dose and virtually unlimited write endurance, making it more attractive than flash memories for space applications. Although a number of manufacturers are(More)
BACKGROUND Many medications administered to patients with schizophrenia possess anticholinergic properties. When aggregated, pharmacological treatments may result in a considerable anticholinergic burden. The extent to which anticholinergic burden has a deleterious effect on cognition and impairs ability to participate in and benefit from psychosocial(More)
1 1 Copyright 1-4244-0525-4/07/$20.00 ©2007 IEEE 2 Final Paper Revision 3, December 7, 2006 Abstract—The Field Programmable Processor Array (FPPA) is a reconfigurable processor chip developed for NASA for high-throughput, low-power on-board processing of streaming data. The FPPA implements a synchronous dataflow computational model, with 16 on-board(More)
This paper describes a project undertaken to simplify the implementation of high-throughput, low-power, numerically intensive applications on Virtex platforms. The system is a pipeline composed of block floating point processing elements. These combine the advantages of fixed-point and floating-point implementations: improved data accuracy (compared to(More)
This paper introduces a reconfigurable processor under development, and targeted to an ultra-low-power, radiation tolerant CMOS process. The architecture has been selected to implement a synchronous pipeline computational model. The highly-parallel, reconfigurable data path emphasizes agile data flow instead of agile control flow for data-intensive,(More)