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This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Hewlett-Packard Company products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new(More)
ASIC, high-level synthesis The PICO-N system automatically synthesizes embedded nonprogrammable accelerators to be used as co-processors for functions expressed as loop nests in C. The output is synthesizable VHDL that defines the accelerator at the register transfer level (RTL). The system generates a synchronous array of customized VLIW (very-long(More)
It is difficult to exploit the massive, fine-grained parallelism of configurable hardware with a conventional application programðming language such as C, Pascal or Java. The difficulty arises from the mismatch between the synchronous, concurrent processing capability of the hardware and the expressiveness of the lanðguage-the so-called "semantic gap." We(More)
Several practical issues in the development and operation of quantum-dot cellular automata (QCA) cells and systems are discussed. The need for adiabatic clocking of QCA systems and modeling of electrostatic confinement of quantum dots are presented. Experimental data on dot coupling and applications to QCA detectors in a 2-dimensional electron gas (2DEG)(More)
1. Abstract Prototypes are invaluable for studying special purpose parallel architectures and custom computing. This paper describes a new FPGA, called Plasma— the heart of a configur-able custom computing engine (Teramac) that can execute synchronous logic designs up to one million gates at rates up to one megahertz. Plasma FPGA's using 0.8 micron CMOS are(More)
This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Hewlett-Packard Company products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new(More)
Accelerating a genetic algorithm (GA) by implementing it in a reconfigurable field programm-able gate array (FPGA) is described. The implemented GA features: random parent selection, which conserves selection circuitry; a steady-state memory model, which conserves chip area; survival of fitter child chromosomes over their less-fit parent chromosomes, which(More)
Random number generators (RNGs) based upon neighborhood-of-four cellular automata (CA) with asymmetrical, non-local connections are explored. A number of RNGs that pass Marsaglia's rigorous Diehard suite of random number tests have been discovered. A neighborhood size of four allows a single CA cell to be implemented with a four-input lookup table and a(More)