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After a long period of academic and industrial research, networks-on-chips (NoCs) are starting to be incorporated into commercial multi-processor designs. NoCs have proven themselves to scale better than bus-based designs and they are here to stay. It is still important to note, however, that even well-designed NoCs consume a large portion of a given(More)
1. Salivary secretions of the stumptail monkey (Macaca arctoides) were compared biochemically and immunologically with human salivas. 2. Similarities in biochemical composition and antigenic profiles as seen by immunoelectrophoresis indicate that monkey salivas can provide an excellent model system to study the role of saliva in the oral ecology of man.
—As the architecture of GPU chips evolves to provide higher performance with lower power, new topology of graphics shader engines interconnection to local frame buffers becomes critical. Source synchronous interconnection has been widely adopted in Network-On-Chip (NoC). The SSB bus fabric to transfer data between shader engines and frame buffers adopts(More)
An asynchronous high-performance low-power 5-port network-on-chip (NoC) router is introduced. The proposed router integrates low-latency input buffers using a circular FIFO design, and a novel end-to-end credit-based virtual channel (VC) flow control for a replicated switch architecture. This asynchronous router is then compared to an AMD synchronous(More)
Data movement along long interconnects in on-chip networks often consume multiple cycles. Such channels incorporate mechanisms for data storage in order to facilitate pipelining. These links can be effectively abstracted as distributed first-in first-out (FIFO) elements. Using the localized timing and flow control made possible by self-timed communication,(More)
The challenges to push computing to exaflop levels are difficult given desired targets for memory capacity, memory bandwidth, power efficiency, reliability, and cost. This paper presents a vision for an architecture that can be used to construct exascale systems. We describe a conceptual Exascale Node Architecture (ENA), which is the computational building(More)
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