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After a long period of academic and industrial research, networks-on-chips (NoCs) are starting to be incorporated into commercial multi-processor designs. NoCs have proven themselves to scale better than bus-based designs and they are here to stay. It is still important to note, however, that even well-designed NoCs consume a large portion of a given(More)
Data movement along long interconnects in on-chip networks often consume multiple cycles. Such channels incorporate mechanisms for data storage in order to facilitate pipelining. These links can be effectively abstracted as distributed first-in first-out (FIFO) elements. Using the localized timing and flow control made possible by self-timed communication,(More)
—As the architecture of GPU chips evolves to provide higher performance with lower power, new topology of graphics shader engines interconnection to local frame buffers becomes critical. Source synchronous interconnection has been widely adopted in Network-On-Chip (NoC). The SSB bus fabric to transfer data between shader engines and frame buffers adopts(More)
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