This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K to 800K gates, pose significant challenges to logic BIST methodology, flow, and tools. The paper presents the process of generating a BIST-compliant core along with the logic BIST… (More)
It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case… (More)
High Speed Serializer Deserializers (serdes) are traditionally tested using functional BIST. This paper presents an improved BIST for testing the digital part of a serdes using circular BIST.
While design-for-test methods such as scan, ATPG, and memory BIST are now well established for ASIC products, their run-time for multi-million gate designs has become a problem. Too often, a tape-out is held up because pattern generation and verification are incomplete. This paper describes a holistic design-for-test approach which exploits both hierarchy… (More)
High-level synthesis has been an active research area for ten years. However, the progress in research has yet to find its way into usage in industry. This paper describes the technology transfer of high-level synthesis at Texas Instruments. It explains how we have extended one research project, the System Architect's Workbench from Carnegie-Mellon… (More)