Gordon Gammie

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For CMOS feature size of 65 nm and below, local (or intra-die or within-die) variations in transistor Vt contribute stochastic variation in logic delay that is a large percentage of the nominal delay. Moreover, when circuits are operated at low voltage (Vdd ≤ 0.5V), the standard deviation of gate delay becomes comparable to nominal delay, and the(More)
This paper describes design features of the high-performance CPU from a heterogeneous tri-cluster, deca-core CPU subsystem incorporated into the Helio X20 mobile SoC for smartphone applications. The SoC is fabricated in a 20nm high-κ metal-gate CMOS, and has a die size of 100mm. Additional key features of the SoC include: a graphics processor unit,(More)
When CMOS is operated at a supply voltage of 0.5V and below, Random Dopant Fluctuations (RDFs) result in a stochastic component of logic delay that can be comparable to the nominal delay. Moreover, the Probability Density Function (PDF) of this stochastic delay can be highly non-Gaussian. The NonLinear, Operating Point Analysis of Local Variations (NLOPALV)(More)
Although numerous clinical trials have demonstrated that cimetidine is efficacious in the treatment of peptic ulcer, fewer studies have examined whether cimetidine reduces the need for surgical therapy when it is prescribed in the noncontrolled environment of clinical medicine. This study reports on the surgical experience in the State of Queensland which(More)