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Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1-4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at(More)
— Interconnections between integrated circuits and print circuit boards are primarily achieved currently with organic packages at high I/O pitch. Organic packages, however, are limited by poor thermal and dimension stabilities for them to act as fine pitch interposers. To address these challenges, silicon interposers are being developed. Current silicon(More)
Smart mobile applications are driving the demand for higher logic-to-memory bandwidth (BW) in 10-30 GB/s range with lower power consumption and larger memory capacity. This paper presents a radically-different, scalable and lower cost approach than the 3D ICs with TSV stack approach being pursued widely, to achieve high bandwidth. This approach is referred(More)
BACKGROUND AND AIMS Continuous arterial pressure monitoring is essential in cardiac surgical patients during induction of general anaesthesia (GA). Continuous non-invasive arterial pressure (CNAP) monitoring is fast gaining importance due to complications associated with the invasive arterial monitoring. Recently, a new continuous non-invasive arterial(More)
Double-sided 3D glass interposers and packages, with through package vias (TPV) at the same pitch as TSVs in Si, have been proposed to achieve high bandwidth between logic and memory with benefits in cost, process complexity, testability and thermal over 3D IC stacks with TSV. However, such a 3D interposer introduces power distribution network (PDN)(More)
— A double-sided and ultrathin 3-D glass interposer with through package vias (TPVs) at same pitch as through silicon vias (TSVs) in silicon interposers is developed to provide a compelling alternative to 3-D IC stacking of logic and memory devices with TSVs. The 3-D IC stacking approach to achieve high bandwidth has several drawbacks, including the need(More)
Transesophageal echocardiography (TEE) has been used routinely in the diagnosis and follow-up of cardiac cases. Left atrial dissection (LAd), an exceedingly rare complication of cardiac surgery, is most commonly associated with mitral valve surgery. A case of LAd is presented, and the pathology was accurately defined and immediately diagnosed using(More)
—This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 μ-diameter, 6 μ-height through-silicon vias (TSVs) and μ-diameter face-to-face bond pads.(More)
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